1. Field of the Invention
The present invention relates to a semiconductor photodetector device, and more particularly, to a technology of measuring an amount of incident light with use of a photodiode.
2. Description of the Related Art
FIG. 3 illustrates a circuit diagram of a conventional semiconductor photodetector device.
The conventional semiconductor photodetector device includes a photodetection section and a counter section.
The photodetection section includes first and second photodiodes 1 and 2, which serve as light receiving elements, first and second storage means 12 and 13, switches 6 and 7, a reference voltage circuit 8a, amplifiers 3 and 4, a difference circuit 5, a clamp capacitor 20, a switch 11, a reference voltage circuit 8b, a comparator 9, and a control circuit 10. The switch 11 and the reference voltage circuit 8b initialize an electric charge of the clamp capacitor 20. The control circuit 10 controls the respective switches in response to reception of an output voltage Vcomp of the comparator 9.
The counter section includes an oscillating circuit 14, a clock shaping circuit 15, first and second counters 16 and 17, a counter reset circuit 18, and a register 19.
The first photodiode 1 is provided with means for blocking infrared light, and generates an electric charge based on incident visible light. The second photodiode 2 is provided with light blocking means for blocking incident light, and generates an electric charge being a reference. The first storage means 12 stores the electric charge generated in the first photodiode 1. The second storage means 13 stores the electric charge generated in the second photodiode 2. The switches 6 and 7 and the reference voltage circuit 8a reset the electric charges stored in the first storage means 12 and the second storage means 13. The difference circuit 5 outputs a voltage based on a difference between the electric charge stored in the first storage means 12 and the electric charge stored in the second storage means 13. The clamp capacitor 20 stores the difference voltage output from the difference circuit 5. The switch 11 and the reference voltage circuit 8b initialize the electric charge of the clamp capacitor 20. The comparator 9 compares a voltage Vout generated based on the difference and a reference voltage Vrefc of a reference voltage circuit 8c, and outputs the voltage Vcomp. That is, when the voltage based on the difference between the electric charge generated based on visible light entering the first photodiode 1 and the electric charge of the second photodiode 2, which is the reference, exceeds the reference voltage Vrefc, the voltage Vcomp is inverted from LOW (Lo) to HIGH (Hi). The control circuit 10 generates a reset signal R and a clamp signal CL in response to reception of the voltage Vcomp output from the comparator 9, and controls the respective switches by those signals.
The oscillating circuit 14 and the clock shaping circuit 15 output a signal TBCLK and a clamp signal CL in response to reception of the clamp signal CL output from the control circuit 10. The signal TBCLK is a signal that is output as a signal of the oscillating circuit 14 only during a period in which the clamp signal CL is Lo. The first counter 16 counts the signal TBCLK, and outputs a signal TBASE1 when the count reaches a predetermined count value. That is, the first counter 16 measures a period in which the photodiodes 1 and 2 store the electric charges based on a frequency of the oscillating circuit. The second counter 17 counts the clamp signal CL, and outputs a count value. That is, the second counter 17 measures the number of cycles of charging and discharging, which are performed by the photodiodes 1 and 2.
FIG. 4 is a timing chart illustrating normal operation of the semiconductor photodetector device.
When a period TBASE is started in the semiconductor photodetector device, the control circuit 10 causes the reset signal R and the clamp signal CL to be Hi.
With this, the switches 6 and 7 are turned ON and the voltages of the photodiodes 1 and 2 are reset to a reference voltage Vrefa. Further, the switch 11 is turned ON and the output of the difference circuit 5 is reset to a reference voltage Vrefb. Then, after the elapse of a predetermined delay time, the control circuit 10 causes the reset signal R to be Lo to turn OFF the switches 6 and 7, and thus the charging of the photodiodes 1 and 2 is started. In the storage period, an output voltage VDI1 of the photodiode 1 decreases in proportion to the amount of incident visible light. Further, the photodiode 2 is shielded from light, and hence an output voltage VDI2 of the photodiode 2 does not decrease.
After the elapse of a period α, the control circuit 10 causes the clamp signal CL to be Lo to turn OFF the switch 11 so that the difference circuit 5 outputs the difference (voltage Vout) to the comparator 9.
The voltage Vout output from the difference circuit 5 gradually increases to reach the reference voltage Vrefc within a difference output period Ts. The difference output period Ts becomes shorter as the visible light intensity is larger.
When the voltage Vout is smaller than the reference voltage Vrefc, the comparator 9 causes the output voltage Vcomp to be Lo, but when the voltage Vout reaches the reference voltage Vrefc within the difference output period Ts, the comparator 9 causes the output voltage Vcomp to be Hi.
When the output voltage Vcomp becomes Hi, the control circuit 10 causes the reset signal R and the clamp signal CL to be Hi, and delays the output signal Vcomp to maintain the Hi state for a predetermined period.
When the reset signal R and the clamp signal CL become Hi, the switches 6, 7, and 11 are turned ON, and the photodiodes 1 and 2 are reset. Thus, the voltage Vout decreases to become the reference voltage Vrefb.
After that, the reset signal R becomes Lo, and subsequently, the clamp signal CL becomes Lo, and then the same operation is repeated.
As described above, the charging and reset of the photodiodes 1 and 2 are repeated, and the difference output period Ts becomes shorter as the visible light intensity is larger.
However, when light containing a large amount of infrared light, such as light of an incandescent bulb, enters the conventional semiconductor photodetector device, or when abnormally intense light enters the conventional semiconductor photodetector device, the conventional semiconductor photodetector device has the following defects.
Depending on the structure of the package of the semiconductor photodetector device, light enters a semiconductor chip from a side surface thereof, and hence a large number of minority carriers are generated in the semiconductor substrate. At this time, due to the minority carriers reaching junction portions between the substrate and the photodiodes 1 and 2, the output voltages VDI1 and VDI2 of the photodiodes 1 and 2 decrease.
When light containing a large amount of infrared light or abnormally intense light enters the semiconductor photodetector device, a reduction amount of the output voltage of the photodiode due to the minority carriers generated by the infrared light or visible light entering the semiconductor chip from the side surface thereof becomes larger in ratio than a reduction amount of the output voltage of the photodiode due to visible light entering the semiconductor chip from the front surface thereof. Therefore, the output voltage VDI1 of the photodiode 1 and the output voltage VDI2 of the photodiode 2 decrease under a state in which the difference therebetween is small. The output voltage VDI1 of the photodiode 1 can decrease only until the junction of the photodiode becomes a forward bias, which is generally about −0.3 V. Therefore, when the reference voltage Vrefa for reset of the photodiodes 1 and 2 is low, the output voltage VDI1 of the photodiode 1 reaches −0.3 V to stop its decrease before the voltage Vout reaches the reference voltage Vrefc. In this case, the output voltage VDI2 of the photodiode 2 further decreases under a state in which the voltage Vout starts decreasing without reaching the reference voltage Vrefc. Therefore, a situation occurs in which the output of the comparator is never inverted during the period TBASE. The semiconductor photodetector device outputs data 0, that is, the detection result shows a dark state even when visible light enters the semiconductor photodetector device.